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? 2014 exar corporation xr77128 quad output digital pwm/pfm universal pmic 1 / 28 exar.com/xr77128 rev 1a general description the xr77128 is a quad channel digital pulse width modulated (pwm) step down (buck) controller. a wide 4.75v to 5.5v and 5.5v to 25v input voltage range allows for single supply operation from standard power rails. with integrated fet gate drivers, two ldos for standby power and a 105khz to 1.23mhz independent channel to channel programmable con- stant operating frequency, the xr77128 reduces overall component count, solution footprint and optimizes conversion efficiencies. a select- able digital pulse frequency mode (pfm) capable of better than 80% effi- ciency at light current load and low operating current allow for portable and energy star compliant applications. each xr77128 channels output voltage is individually programmable down to 0.6v with a resolution of 2.5mv, and is configurable for precise soft start and soft stop sequencing, including delay and ramp control. the xr77128 operations are fully controlled via a smbus-compliant i 2 c interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as well as fault handling. built-in independent output over-voltage, over-temperature, over-cur- rent and under-voltage lockout protections insure safe operation under abnormal operating conditions. the xr77128 is offered in a rohs compliant, green/halogen free 44-pin tqfn package. features ? quad channel step-down controller ? digital pwm 105khz-1 .23mhz operation ? individual channel frequency selection ? patented digital pfm with ultrasonic mode ? patented over sampling feedback ? programmable 5 coeffi cient pid control ? integrated mosfet drivers ? supports drmos devices ? 4.75v to 5.5v and 5.5v to 25v input voltage ? 0.6v to 5.5v output voltage (higher with exter- nal feedback resistors) ? smbus compliant i 2 c interface ? full power monitoring and reporting ? 3 x 15v capable psio + 2 x gpios ? full start/stop sequencing support ? built-in thermal, over-c urrent, uvlo and out- put over-voltage protections ? on board 5v and ldoout standby ldos ? on board non-volatile memory ? supported by powerarchitect? 5.2 or later applications ? industrial control systems ? automatic test equipment ? video surveillance systems ? automotive infotainment ordering information C back page typical application
? 2014 exar corporation xr77128 2 / 28 exar.com/xr77128 rev 1a absolute maximum ratings stresses beyond the limits listed below may cause perma- nent damage to the device. exposure to any absolute max- imum rating condition for extended periods may affect device reliability and lifetime. vccd, ldo5, ldoout, glx, voutx........................-0.3v to 7.0v enable, v5ext.........................................................-0.3v to 7.0v gpio0/1, scl, sda.................................................................6.0v psio inputs, bfb......................................................................18v dvdd, avdd...........................................................................2.0v vcc..........................................................................................28v lx#.................................................................................-1v to 28v bstx, ghx........................................................................vlx + 6v storage temperature.............................................-65c to +150c power dissipation................................................internally limited lead temperature (soldering, 10 sec)..................................300c esd rating (hbm - human body model)............... ........... .......2kv operating conditions input voltage range vcc............... .............. ............ ....5.5v to 25v input voltage range vcc = ldo5.... ........... ........... ...4.75v to 5.5v vout1, 2, 3, 4.........................................................................5.5v junction temperature range................................-40c to +125c jedec thermal resistance ? ja .........................................32c/w electrical characteristics unless otherwise noted: t j = 25c, vcc = 5.5v to 25v, v5ext open. limits applying over the full operating temperature range are denoted by a ? symbol parameter conditions min typ max units quiescent current i supply vcc supply current shutdown en = 0v, vcc = 12v 10 20 a standby i/os programmed as inputs, vcc = 12v, en = 5v 550 650 a 2ch pfm 2 channels on set at 5v, vout forced to 5.1v, no load, non-switching, ultra-sonic off, vcc = 12v, no i 2 c activity 3.1 ma 4ch pfm 4 channels on set at 5v, vout forced to 5.1v, no load, non-switching, ultra-sonic off, vcc = 12v, no i 2 c activity 4.0 ma 4ch pwm all channels enabled, f sw = 600khz, gate drivers unloaded, no i 2 c activity 18 ma
? 2014 exar corporation xr77128 3 / 28 exar.com/xr77128 rev 1a v enable enable turn on threshold vcc = 12v, enable rising 0.65 0.95 v i leak enable pin leakage current en = 5v 3.6 10 a en = 0v -10 a input voltage range and undervoltage lockout vcc vcc range ? 5.5 25 v with vcc connected to ldo5 ? 4.75 5.5 v voltage feedback accuracy and output voltage set point resolution v a_vo vout regulation accuracy low output range 0.6 vout 1.6v, pwm operation -5 5 mv ? -12.5 12.5 mv mid output range 0.6 vout 3.2v, pwm operation -10 10 mv ? -25 25 mv high output range 0.6 vout 5.5v, pwm operation -20 20 mv ? -50 50 mv v r_vo vout regulation range without external divider network ? 0.6 5.5 v v native vout native set point resolution low range 12.5 mv mid range 25 mv high range 50 mv v fine vout fine set point resolution 1 low range 2.5 mv mid range 5 mv high range 10 mv r in vout input resistance low range 120 k mid range 80 k high range 65 k r in vout input resistance in pfm low range 10 m mid range 1 m high range 0.67 m v set_pg power good and ovp set point range (from set point) low range -155 157.5 mv mid range -310 315 mv high range -620 630 mv v set_pg power good and ovp set point accuracy low range -5 5 mv mid range -10 10 mv high range -20 20 mv v set_bf bfb set point range 916v v res_bf bfb set point resolution 1v v a_bf bfb accuracy -0.5 0.5 v symbol parameter conditions min typ max units
? 2014 exar corporation xr77128 4 / 28 exar.com/xr77128 rev 1a current and aux adc (monitoring adcs) v a_cs current sense accuracy low range (120mv), -60mv applied -2.5 1.25 2.5 mv ? -6.25 6.25 mv high range (280mv), 150mv applied -5 2.5 5 mv ? -12.5 12.5 mv inl cs current sense adc inl 0.4 lsb dnl cs current sense dnl 0.4 lsb v set_cs current limit set point resolution and current sense adc resolution low range (120mv) 1.25 mv high range (280mv) 2.5 mv v cs current sense adc range low range (120mv) -120 20 mv high range (280mv) -280 40 mv v adc_vo vout adc resolution low range 15 mv mid range 30 mv high range 60 mv lsb adc vout adc accuracy -1 1 lsb v adc vcc adc range 4.6 25 v v r_adc vcc adc resolution 200 mv v a_adc vcc adc accuracy vcc 20v -1 1 lsb t r_adc die temp adc resolution 5c t adc die temp adc range output value is in kelvin -44 156 c linear regulators v o_ldo5 ldo5 output voltage 5.5v vcc 25v 0ma < i ldo5out < 130ma, ldoout off ? 4.85 5.0 5.15 v i cl_ldo5 ldo5 current limit ldo5 fault set ? 135 155 180 ma ldo5 uvlo vcc rising ? 4.6 v ldo5 pgood hysteresis vcc falling 375 mv ldo5 bypass switch resistance 1. 1 1. 5 bypass switch activation threshold v5 ext rising, % of threshold setting ? 2.5 2.5 % bypass switch activation hysteresis v5ext falling 150 mv ldoout output voltage 4.6v ldo5 5.5v 0ma < i ldoout < 50ma ldoout set to 3.3v ? 3.15 3.3 3.45 v ldoout current limit ldoout fault set, ldoout set to 3.3v ? 50 85 ma maximum total ldo loading during enable start-up enable transition from logic low to high. once ldo5 in regulation, above limits apply. 75 ma symbol parameter conditions min typ max units
? 2014 exar corporation xr77128 5 / 28 exar.com/xr77128 rev 1a pwm generators and oscillator f sw switching frequency range steps defined in table 105 1230 khz switching frequency accuracy -5 5 % f clkin clock in synchronization fre- quency when synchronizing to an external clock (range 1) 20 25.7 31 mhz when synchronizing to an external clock (range 2) 10 12.8 15.5 mhz i 2 c and gpios 2 v il input pin low level 0.8 v v ih input pin high level 1. 3 5 v input pin leakage current 1a v ol output pin low level i sink = 1ma 0.4 v v oh output pin high level i source = 1ma 2.4 v i source = 0ma 3.3 3.6 v output pin high-z leakage current (gpio pins only) 10 a maximum sink current open drain mode 1 ma i/o frequency 30 mhz psios 3 v il input pin low level 0.8 v v ih input pin high level psio0 and psio1 2 v v ih input pin high level psio2 1.35 v input pin leakage current 1a v ol output pin low level i sink = 3ma 0.4 v v oh output pin high level open drain. external pull-up resistor to user supply. 15 v output pin high-z leakage current (psio pins only) 10 a i/o frequency 5mhz smbus (i 2 c) interface v il input pin low level v io = 3.3v 10% 0.3v io v v ih input pin high level v io = 3.3v 10% 0.7v io v v hys hysteresis of schmitt trigger inputs v io = 3.3v 10% 0.05 v io v v ol output pin low level (open drain or collector) i sink = 3ma 0.4 v i leak input leakage current input is between 0.1v io and 0.9v io -10 10 a symbol parameter conditions min typ max units
? 2014 exar corporation xr77128 6 / 28 exar.com/xr77128 rev 1a note 1: fine set point resolution not available in pfm note 2: 3.3v cmos logic compatible, 5v tolerant note 3: 3.3v/5.0v cmos logic compatible, maximum rating of 15.0v output fall time from v ihmin to v il- max with a bus capacitance (c b ) from 10pf to 400pf 20 + 0.1c b 250 ns internal pin capacitance 1pf gate drivers gh, gl rise time at 10-90% of full scale, 1nf cload 17 ns gh, gl fall time at 10-90% of full scale, 1nf cload 11 ns gh, gl pull-up on-state output resistance 4.35 5 gh, gl pull-down on-state output resistance 1.96 2.5 gh, gl pull-down off-mode resis- tance vcc = vccd = 0v 48 k bootstrap diode forward resistance at 10ma 8.5 minimum on-time 1nf of gate capacitance 50 ns minimum off-time 1nf of gate capacitance 125 ns minimum programmable dead time does not include dead time variation from driver output stage, t sw = switching period 20 ns maximum programmable dead time t sw programmable dead time adjust- ment step 103mhz internal clock frequency 607 ps symbol parameter conditions min typ max units
? 2014 exar corporation xr77128 7 / 28 exar.com/xr77128 rev 1a pin configuration pin assignments pin no. pin name description 1 ldoout output of the standby ldo. this is a micr o power ldo that needs to be configured or com- manded to turn on. 2 agnd analog ground pin. this is the small signal ground connection. 3 cpll connect to a 2.2nf capacitor to gnd. 4 avdd output of the internal 1.8v ldo. a decoupling capacitor should be placed between avdd and agnd close to the chip. 5, 6, 7, 8 vout1, vout2, vout3, vout4 connect to the output of the corresponding power stage.the out put is sampled at least once every switching cycle. 9,10 gpio0, gpio1 these pins can be configured as inputs or outputs to implement custom flags, power good sig- nals, enable/disable controls and synchronization to an external clock. 11, 12 sda, scl smbus/i 2 c serial interface communication pins.
? 2014 exar corporation xr77128 8 / 28 exar.com/xr77128 rev 1a 13, 14, 15 psio0, psio1, psio2 open drain, these pins can be used to control external power mosfets to switch loads on and off, shedding the load for fine grained power m anagement. they can also be configures as standard logic outputs or inputs just as any of the gpios can be configured, but as open drains require an external pul l-up when configured as outputs. 16 dvdd 1.8v supply input for digital circuitry. c onnect pin to avdd. place a decoupling capacitor close to the controller ic. 17 dgnd digital ground pin. this is the logic ground connection, and should be connected to the ground plane close to the pad. 18, 24, 29, 35 bst4, bst3, bst2, bst1 high side driver supply pin(s). connect bst to the external capacitor as shown in the typical application circuit. the high side driver is connected between the bst pin and lx pin and delivers the bst pin voltage to the high side fet gate each cycle. 19, 25, 30, 36 gh4, gh3, gh2, gh1 output pin of the high side gate driver. connect directly to the gate of an external n-channel mosfet. 20, 26, 31, 37 lx4, lx3, lx2, lx1 lower supply rail for the gh high-si de gate driver. connect this pin to the switching node at the junction between the two external power mosf ets and the inductor. these pins are also used to measure voltage drop across bottom mosfets in order to provide output current information to the control engine. 21, 27, 32, 38 gl4, gl3, gl2, gl1 output pin of the low side gate driv er. connect directly to the gate of an external n-channel mosfet. 22, 28, 33, 39 gl_rtn4, gl_rtn3, gl_rtn2, gl_rtn1 ground connection for the low side gate driver. this should be routed as a signal trace with gl. connect to the source of the low side mosfet. 23, 34 vccd3-4, vccd1-2 gate drive supply. two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 and 4. one of th e two pins must be connected to the ldo5 pin to enable two power rails initially. it is recommended that the other vccd pin be connected to the output of a 5v switching rail (for improved effi ciency or for driving lar ger external fets), if available, otherwise this pin may also be conn ected to the ldo5 pin. a bypass capacitor (>1uf) to the system ground is recommended for each vccd pin with the pin(s) connected to ldo5 with shortest possible length of etch. 40 enable if enable is pulled high or allowed to float hi gh, the chip is powered up (logic is reset, regis- ters configuration loaded, etc.). the pin must be held low for the xr77128 to be placed into shutdown. 41 vcc input voltage. place a decoupling capacitor close to the controll er ic. this input is used in uvlo fault generation. 42 bfb input from the 15v output created by the external boost supply. when this pin goes below a pre-defined threshold, a pulse is created on the low side drive to charge this output back to the original level. if not used, th is pin should be connected to gnd. 43 v5ext external 5v that can be provided. if one of the output channels is configured for 5v, then this voltage can be fed back to this pin for reduced operating current of the chip and improved effi- ciency. 44 ldo5 output of a 5v ldo. this ldo is used to power the internal analog blocks. 45 pad this is the die attach paddle, which is expos ed on the bottom of the part. connect externally to the ground plane. pin no. pin name description
? 2014 exar corporation xr77128 9 / 28 exar.com/xr77128 rev 1a functional block diagram xr77128 block diagram ldo block diagram
? 2014 exar corporation xr77128 10 / 28 exar.com/xr77128 rev 1a typical performance characteristics unless otherwise noted: vcc = 12v, t a = 25c figure 1: pfm to pwm transition figure 2: pwm to pfm transition figure 3: 0-6a transient 300khz pwm only figure 4: 0-6a transient 300khz with ovs +/-5% figure 5: pfm zero current accuracy figure 6: ldo5 brown out recovery, no load
? 2014 exar corporation xr77128 11 / 28 exar.com/xr77128 rev 1a figure 7: sequential, conditional start-up figure 8: sequential, conditional shut-down figure 9: simultaneous start-up figure 10: simultaneous shut-down figure 11: ramp-up rate dynamic sweep figure 12: ramp-down rate dynamic sweep
? 2014 exar corporation xr77128 12 / 28 exar.com/xr77128 rev 1a figure 13: start-up delay dynamic sweep figure 14: shut-down delay dynamic sweep figure 15: shut-down current versus vcc figure 16: enable threshold over temperature at vcc=12v
? 2014 exar corporation xr77128 13 / 28 exar.com/xr77128 rev 1a functional description overview the xr77128 is a quad-output digital pulse width modula- tion (pwm) controller with integrated gate drivers for use with synchronous buck switching regulators. each output voltage can be programmed from 0.6v to 5.5v without the need for an external voltage divider. the wide range of pro- grammable pwm switching frequency (from 105 khz to 1.2 mhz) enables the user to optimize for efficiency or compo- nent sizes. since the digital regulation loop requires no external passive components, loop performance is not compromised due to external component variation or oper- ating condition. the xr77128 provides a number of critical safety features such as over-current protection (ocp), over-voltage pro- tection (ovp), over-temperature protection (otp), plus input under-voltage lockout (uvlo). in addition, it has a number of key health monitoring features such as warning level flags for the safety functions, power good (pgood), etc., plus full monitoring of system voltages and currents. the above are all programmable and/or readable from the smbus and many are steerable to the ios for hardware monitoring. for hardware communication, the xr77128 has two logic level general purpose input-output (gpio) pins and three 15v, open drain, power system input-output (psio) pins. two pins are dedicated to the smbus data (sda) and clock (scl). additional pins include chip enable (enable), aux boost feedback (bfb) and external pll capacitor (cpll). in addition to providing four switching outputs, the xr77128 also provides control for an aux boost supply, and two stand-by linear regulators for a total of seven customer usable supplies in a single device. the 5v ldo is used for internal power and is also available for customer use to power external circuitry. ldoout is solely for customer use and is not used by the chip. there is also a 1.8v linear regulator which is for internal use only and should not be used externally. a key feature of the xr77128 is its advanced power man- agement capabilities. all f our outputs ar e independently programmable and provide the user full control of the delay, ramp, and sequence during power up and power down. the user may also control how the outputs interact and power down in the event of a fault. this includes active ramp down of the output voltages to remove an output voltage as quickly as possible. another useful feature is that the out- puts can be defined and controlled as groups. the xr77128 has two main types of programmable mem- ory. the first type is runtime registers that contain configu- ration, control and monitoring information for the chip. the second type is rewritable non- volatile flash memory that is used for permanent storage of the configuration data along with various chip internal functions. during power up, the run time registers are loaded from the flash memory allow- ing for standalone operation. the xr77128 brings an extremely high level of functionality and performance to a programmable power system. ever decreasing product budgets require the designer to quickly make good cost/performance tradeoffs to be truly success- ful. by incorporating 4 switching channels, two user ldos, a charge pump boost controller, along with internal gate drivers, all in a single package, the xr77128 allows for extremely cost effective power system designs. another key cost factor that is often overlooked is the unanticipated engineering change order (eco). the programmable ver- satility of the xr77128, along with the lack of hard wired configuration components, allows for minor and major changes to be made in circuit by simple reprogramming.
? 2014 exar corporation xr77128 14 / 28 exar.com/xr77128 rev 1a regulation loops figure 17: regulation loops figure 17 shows a simplified functional block diagram of the regulation loops for one output channel of the xr77128. there are four separate parallel control loops: pulse width modulation (pwm), pulse frequency modulation (pfm), ultrasonic, and over sampling (ovs). each of these loops is fed by the analog front end (afe) as shown at the left of the diagram. the afe consist of an input voltage scaler, a programmable voltage reference (vref) dac, error ampli- fier, and a window comparator. some of the functional blocks are common and shared by each channel by means of a multiplexer. pwm loop the pwm loop operates in voltage control mode (vcm) with optional vin feed forward based on the voltage at the vcc pin. the reference voltage (vref) for the error amp is created by a 0.15v to 1.6v dac that has a 12.5mv resolu- tion. in order to provide a 0.6v to 5.5v output voltage range, an input scaler is used to reduce feedback voltages for higher output voltages to bring them within the 0.15v to 1.6v control range. so for output voltages up to 1.6v (low range), the scaler has a gain of 1. for output voltages from 1.6v to 3.2v (mid range) the scalar gain is 1/2, and for volt- ages greater than 3.2v (high range) the gain is 1/4. this results in the low range having a reference voltage resolu- tion of 12.5mv, the mid range having a resolution of 25mv, and the high range having a resolution of 50mv. the error amp has a gain of 4 and compares the output voltage of the scaler to vref to create an error voltage on its output. this is converted to a digital error term by the afe adc and is stored in the error register. the error register has a fine adjust function that can be used to improve the output volt- age set point resolution by a factor of 5 resulting in a low range resolution of 2.5mv, a mid range resolution of 5mv and a high range resolution of 10mv. the output of the error register is then used by the proportional integral derivative (pid) controller to manage the loop dynamics. the xr77128 pid is a 17-bit five-coefficient control engine that calculates the required duty cycle under the various operating conditions and feeds it to the digital pulse width modulator (pwm). besides the normal coefficients, the pid also uses the vcc voltage to provide a feed forward func- tion. the xr77128 digital pwm includes a special delay timing loop that provides a timing resolution that is 16 times the master oscillator frequency (103mhz) for a timing resolution of 607ps for both the driver pulse width and dead time delays. the pwm produces the gate high (gh) and gate low (gl) signals to the driver. the maximum and minimum on times and dead time delays are programmable by con- figuration resisters. to provide current information, the output inductor current is measured by a differential amplifier that reads the voltage drop across the rdson of the synchronous fet during its on time. there are two selectable ranges, a low range with a gain of 8 for a -120mv to +20mv voltage range, and a high range with a gain of 4 for -280mv to +40mv voltage range. the optimum range to use will depend on the maxi- mum output current and the rdson of the synchronous fet. the measured voltage drop is then converted to a dig- ital value by the current adc block. the resulting current
? 2014 exar corporation xr77128 15 / 28 exar.com/xr77128 rev 1a value is stored in a readable register and also used to determine when pwm to pfm transitions should occur. pfm loop the xr77128 has a pfm loop that can be enabled to improve efficiency at light loads. by reducing switching fre- quency and operating in the discontinuous conduction mode (dcm), both switching and conduction losses are minimized. figure 18 shows a functional diagram of the pfm logic. figure 18: pfm enter/exit functional diagram the pfm loop works in conjunction with the pwm loop and is entered when the output current falls below a pro- grammed threshold level for a programmed number of cycles. when pfm mode is entered, the pwm loop is dis- abled and instead, the scaled output voltage is compared to vref with a window comparator. the window comparator has three thresholds; normal (vref), high (vref + %high) and low (vref - %low). the %high and %low values are pro- grammable and track vref. in pfm mode, the normal comparator is used to regulate the output voltage. if the output voltage falls below the vref level, the comparator is activated and triggers the pwm to start a switching cycle. when the switching fet is turned on, the inductor current ramps up which charges up the out- put capacitors and increases their voltage. after the com- pletion of the high side and low side on-times, the synchronous fet is turned off to inhibit any inductor reverse current flow. the load current then discharges the output capacitors until the output voltage falls below vref and the normal comparator is activated. this triggers the pwm to start the next switching cycle. the time from the end of the switching cycle to the next trigger is referred to as the dead zone. when pfm mode is initially entered, the switching cycle is equal to the steady-state pwm duty cycle.this will cause the inductor ripple current to be at the same level that is in pwm mode of operation. during oper- ation the pfm duty cycle is calculated based on the ratio of the output voltage to vcc. this method ensures that the output voltage ripple is well controlled and is much lower than in other architectures which use a burst methodol- ogy. if the output voltage ever goes outside the high/low win- dows, pfm mode is exited and the pwm loop is reacti- vated. although the pfm mode is effective at improving efficiency at light load, at very light loads the dead zone time can increase to the point where the switching frequency can enter the audio hearing range. when this happens some components, like the output inductor and ceramic capaci- tors, can emit audible noise. the amplitude of the noise depends mainly on the board design and on the manufac- turer and construction details of the components. proper selection of components can reduce the sound to very low levels. in general ultrasonic mode is not used unless required as it reduces light load efficiency. ultrasonic mode ultrasonic mode is an extension of pfm to ensure that the switching frequency never enters the audible range. when this mode is entered, the switching frequency is set to 30khz and the duty cycle of the switching and synchronous fets which are fixed in pfm mode, are decreased as required to keep the output voltage in regulation while maintaining the 30khz switching frequency. under extremely light or zero load currents, the gh on time pulse width can decrease to its minimum width. when this happens, the synchronous fet on time is increased slightly to allow a small amount of reverse inductor current to flow back into vin to keep the output voltage in regulation while maintaining the switching frequency above the audio range. oversampling (ovs) mode oversampling (ovs) mode is a feature added to the xr77128 to improve transient responses. this mode can only be enabled when the channel switching frequency is operating in 1x frequency mode. in ovs mode, the output voltage is sampled 4 times per switching cycle and is moni- tored by the afe window comparator. if the voltage goes outside the set high or low limits, the ovs control electron- ics can immediately modify the pulse width of the gh or gl drivers to respond accordingly without having to wait for the next cycle to start. ovs has two types of response depend- ing on whether the high limit is exceeded during an unload- ing transient (over voltage), or the low limit is exceeded during a loading transient (under voltage). # cycles reg default = 20 pfm current threshold reg a a ? 2014 exar corporation xr77128 16 / 28 exar.com/xr77128 rev 1a under voltage ovs : if there is an increasing current load step, the output voltage will drop until the regulator loop adapts to the new conditions to return the voltage to the correct level. depending on where in the switching cycle the load step happens there can be a delay of up to one switch- ing cycle before the control loop can respond. with ovs enabled if output voltage drops below the lower limit of the window comparator, an immedi ate gh pulse will be gener- ated and sent to the driver to increase the output inductor current toward the new load level without having to wait for the next cycle to begin. if the output voltage is still below the lower limit of the window comparator at the beginning of the next cycle, ovs will work in conjunction with the pid to insert additional gh pulses to quickly return the output volt- age back within its regulation band. the result of this sys- tem is transient response cap abilities on par or exceeding those of a constant on-time control loop. over voltage ovs : when there is a step load current decrease, the output voltage w ill increase (bump up) as the excess inductor current that is no longer used by the load, flows into the output capacitors causing the output voltage to rise. the voltage will continue to rise until the inductor current decreases to the new load current level. with ovs enabled, if the output voltage exceeds the high limit of the window comparator, a blanking pulse is generated to trun- cate the gh signal. this causes inductor current to immedi- ately begin decreasing to the new load level. the gh signal will continue to be blanked until the output voltage falls below the high limit of the window comparator. again, since the output voltage is sampled at four times the switching frequency, overshoot will be decreased and the time required to get back into the regulation band is also decreased. ovs can be used in conjunction with both the pwm and pfm operating modes. when it is activated it can notice- ably decrease output voltage excursions when transitioning between pwm and pfm modes. internal drivers the internal high and low gate drivers use totem pole fets for high drive capability. they are powered by two external 5v power pins (vccd1-2) and (vccd3-4). vccd1-2 pow- ers the drivers for channels 1 and 2 while vccd3-4 powers channels 3 and 4. the drivers can be powered by the inter- nal 5v ldo by connecting their power pins to the ldo5 output through an rc filter to avoid conducted noise back into the analog circuitry. to minimize power dissipation in the 5v ldo, it is recom- mended to power the drivers from an external 5v power source either directly or by using the v5ext input. good quality 1uf to 4.7uf capacitors should be connected directly between the power pins to ground to optimize driver performance and minimize noise coupling to the 5v ldo supply. the driver outputs should be connected directly to their cor- responding output switching fets with the lx output con- nected to the drain of the synchronous fet for the best current monitoring accuracy. see anp-32 practical layout guidelines for powerxr designs ldos the xr77128 has two internal low drop out (ldo) linear regulators that generate 5.0v (ldo5) and configurable volt- age (ldoout) for both internal and external use. xr77128 can be programmed to four ldoout output voltage set- tings, 3.3v, 2.8v, 2.5v and 1.8v. additionally, xr77128 has a 1.8v regulator that supplies power for the xr77128 inter- nal circuits. ldo5 is the main power input to the device and is supplied by an external 5.5v to 25v (vcc) supply. the output of ldo5 should be bypassed by a good quality 4.7uf or larger capacitor connected between the pin and ground close to the device. the 5v output is used by the xr77128 as a standby power supply and is also used to power the ldoout and 1.8v linear regulators inside the chip, and can also supply power to the 5v gate drivers. the total output current that the 5v ldo can provide is 130ma. the xr77128 consumes approximately 20ma and the rest is shared between ldoout and the gate drive currents. the ldoout output available on the ldoout pin is solely for customer use and is not used internally. this supply is turned on or off by the configuration registers. again a good bypass capacitor should be used. the avdd pin is the 1.8v regulator output and needs to be connected externally to the dvdd pin on the device. a good quality capacitor should be connected between this pin and ground close to the package.
? 2014 exar corporation xr77128 17 / 28 exar.com/xr77128 rev 1a clocks and timing figure 19: xr77128 timing block diagram figure 19 shows a simplified block diagram of the xr77128 timings. again, please note that the function blocks and sig- nal names used are chosen for ease of understanding and do not necessarily reflect the actual device design. the system timing is generated by a 103mhz internal sys- tem clock (sys_clk). there are two ways that the 103 mhz system clock can be generated. these include an internal oscillator and a phase locked loop (pll) that is synchro- nized to an external clock input. the basic timing architec- ture is to divide the sys_clk down to create a fundamental switching frequency (fsw_fund) for all the output channels that is settable from 105khz to 306khz. the switching fre- quency for a channel (fsw_chx) can then be selected as 1 time, 2 times or 4 times the fundamental switching fre- quency. to set the base frequency for the output channels, an fsw_set value representing the base frequency shown in table 1 is entered into the switching frequency configuration register. note that fsw_set value is basically equal to the sys_clk divided by the base frequency. the system timing is then created by dividing down sys_clk to produce a base frequency clock, 2x and 4x times the base frequency clocks, and sequencing timing to position the output chan- nels relative to each other. each output channel then has its own frequency multiplier register that is used to select its final output switching frequency. table 1 shows the available channel switching frequencies for the xr77128 device. in practice the powerarchitect? 5.2 (pa 5.2) design tool handles all the details and the user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency multiplier for each channel. if an external clock is used, the frequencies in this table will shift according to percentage of frequency deviation between the clock supplied and nominal value for a given locking range.
? 2014 exar corporation xr77128 18 / 28 exar.com/xr77128 rev 1a note: some table entries are affected by rounding. supervisory and control power system design with xr77128 is accomplished using powerarchitect? design tool version 5.2 or later (pa 5.2). all figures referenced in the following sections are taken from pa 5.2. furthermore, the following sections reference i 2 c commands. for more information on these commands refer to anp-38. digital i/o xr77128 has two general purpose input output (gpio) and three power system input output (psio) user configu- rable pins. ? gpios are 3.3v cmos logic compatible and 5v toler- ant. ? psios configured as outputs are open drain and require external pull-up resistors. these i/os are 3.3v and 5v cmos logic compatible, and up to 15v capable. the polarity of the gpio/psio pins is set in pa 5.2 or with an i 2 c command. table 1: available channel switching frequencies base frequency (khz) available 2x frequencies (khz) available 4x frequencies (khz) 105.5 211.1 422.1 107.3 214.6 429.2 109.1 218.2 436.4 111. 0 222.0 444.0 112.9 225.9 451.8 115 . 0 229.9 459.8 117.0 234.1 468.2 119 . 2 238.4 476.9 121.5 242.9 485.8 123.8 247.6 495.2 126.2 252.5 504.9 128.8 257.5 515.0 131.4 262.8 525.5 134.1 268.2 536.5 137.0 273.9 547.9 139.9 279.9 559.8 143.1 286.1 572.2 146.3 292.6 585.2 149.7 299.4 598.8 153.3 306.5 613.1 157.0 314.0 628.0 160.9 321.9 643.8 165.1 330.1 660.3 169.4 338.8 677.6 174.0 348.0 695.9 178.8 357.6 715.3 183.9 367.9 735.7 189.3 378.7 757.4 195.1 390.2 780.3 201.2 402.3 804.7 207.7 415.3 830.6 214.6 429.2 858.3 222.0 444.0 887.9 229.9 459.8 919.6 238.4 476.9 953.7 247.6 495.2 990.4 257.5 515.0 1030.0 268.2 536.5 1072.9 279.9 559.8 1119.6 292.6 585.2 1170.5 306.5 613.1 1226.2 table 1: available channel switching frequencies base frequency (khz) available 2x frequencies (khz) available 4x frequencies (khz)
? 2014 exar corporation xr77128 19 / 28 exar.com/xr77128 rev 1a configuring gpio/psios the following functions can be controlled from or forwarded to any gpio/psio: ? general output C set with an i 2 c command ? general input C triggers an interrupt; state read with an i 2 c command ? power group enable C controls enabling and disabling of channels placed in group 1and group 2 ? power channel enable C controls enabling and dis- abling of a individual channel including ldoout ? i 2 c address bit C controls an i 2 c address bit ? power ok C indicates that selected channels have reached their target levels and have not faulted. multiple channel selection is available in which case the resulting signal is the and logic function of all channels selected ? resetout C is delayed power ok. delay is programma- ble in 5ms increments with the range of 0 to 255ms. when no channels selected, the transition will indicate the controller has finished the booting process and is ready to communicate. ? low vcc C indicates when vcc has fallen below the uvlo fault threshold and when the uvlo condition clears (vcc voltage rises above the uvlo warning level) ? interrupt C the controller generated interrupt selection and clearing is done through i 2 c commands ? hw power good C the power good hardware monitor- ing function. it is an output voltage monitoring function that is a hardware comparison of channel output voltage against its user defined power good threshold limits (power good minimum and maximum levels). it has no hysteresis. multiple channel selection will be combined using the and logic function of all channels selected. the power good minimum and maximum levels are expressed as percentages of the target voltage. pgood max is the upper window and pgood min is the lower window. the minimum and maximum for each of these values can be calculated with the following equation: where n=1 to 63 for the pgood max value, and n=1 to 62 for the pgood min value. for example, with the target volt- age of 1.5v and set point resolution of 2.5mv (lsb), the power good min and max values can range from 0.17% to 10.50% respectively. a user can effectively double the power good range by changing to the next higher output voltage range setting, but at the expense of reduced set point resolution. interrupt, low vcc, power ok and resetout signals can only be forwarded to a single gpio/psio. in addition, the following are functions that are unique to gpio0 and gpio1. ? hw flags C these are hardware monitoring functions forwarded to gpio0 only. the functions include under- voltage lockout warning, over-temperature warning, over-voltage fault, over-current fault and over-current warning for every channel. multiple selections will be combined using the or logic selected function. a subset of hardware flags which includes under-voltage lockout warning, over-temperature warning, and over- voltage fault for every channel is available on the other i/ os. pgood (%) n lsb (mv) 10 5 ? ? vtarget (v) ------------------ ------------------ -------------- =
? 2014 exar corporation xr77128 20 / 28 exar.com/xr77128 rev 1a ? external clock-in C enables the controller to lock to an external clock including one from another xr77128 applied to the gpio0 pin. there are two ranges of clock frequencies the controller accepts, selectable by a user. ? external clock-out C clock sent out through gpio1 for synchronizing with another xr77128 (see the clock out section for more information). fault handling there are seven different types of fault handling in xr77128: ? under voltage lockout (uvlo) monitors voltage sup- plied to the vcc pin and will cause the controller to shutdown all channels if the supply drops to critical lev- els. ? over temperature protection (otp) monitors tem- perature of the chip and will cause the controller to shut- down all channels if temperature rises to critical levels. ? over voltage protection (ovp) monitors regulated volt- age of a channel and will cause the controller to react in a user specified way if the regulated voltage surpasses threshold level. ? over current protection (ocp) monitors current of a channel and will cause the c ontroller to react in a user specified way if the current level surpasses threshold level. ? start-up time-out fault monitors whether a channel gets into regulation in a user defined time period. ? ldo5 over current protection (ldo5 ocp) monitors current drawn from the regulator and will cause the con- troller to be reset if the current exceeds ldo5 limit. ? ldoout over current protection (ldoout ocp) monitors current drawn from the regulator and will cause the controller to shut down the regulator if the current exceeds ldoout limit. uvlo both uvlo warning and fault levels are user programmable and set at 200mv increments in pa 5.2. when the warning level is reached the controller will gener- ate the uvlo_warning_event interrupt. in addition, the host can be informed about the event through hw flags (see the digital i/o section). when an uvlo fault condition occurs, the xr77128 out- puts are shut down and the uvlo_fault_ac- tive_event interrupt is genera ted. in addition, the host can be informed by forwarding the low vcc signal to any gpio/psio (see the digital i/o section). this signal transi- tions when the uvlo fault occurs. when coming out of the fault, rising vcc crossing the uvlo fault level will trigger the uvlo_fault_inactive_event interrupt. once uvlo condition clears (v cc voltage rises to or above the user defined uvlo warning level), the low vcc signal will transition and the co ntroller will be reset. otp user defined otp warning, fault and restart levels are set at 5c increments in pa 5.2. when the warning level is reached the controller will gener- ate the temp_warning_event interrupt. in addition, the host can be informed about the event through hw flags (see the digital i/o section). when an otp fault condition occurs, the xr77128 outputs are shutdown and the temp_over_event interrupt is generated. once temperature reaches a user defined otp restart threshold level, the temp_under_event interrupt will be generated and the controller will reset. ovp a user defined ovp fault level is set in pa 5.2 and is expressed in percentages of a regulated target voltage. resolution is the same as for the target voltage (expressed in percentages). the ovp minimum and maximum values are calculated by the following equation where the range for n is 1 to 63: ovp (%) n lsb (mv) 10 5 ? ? vtarget (v) ---------------- ----------------- ----------------- =
? 2014 exar corporation xr77128 21 / 28 exar.com/xr77128 rev 1a when the ovp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. in addition, ovp fault can be monitored through any i/o. a user can choose one of three options in response to an ovp event: to shutdown the faulting channel, to shut down faulting channel and to perform auto-restart of the channel, or to restart the chip. choosing the restart chip option during development is not recommended as it makes debug efforts difficult. for the case of shutdown and auto-restart channel, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) peri- ods in 1 ms increments with a maximum value of 255 ms. note: the channel fault action response is the same for an ovp or ocp event. ocp a user defined ocp fault level is set with 10ma increments in pa 5.2. pa 5.2 uses calculations to give the user the approximate dc output current entered in the current limit field. however, the actual current limit trip value pro- grammed into the part is limited to 280mv as defined in the electrical characteristics. the maximum value the user can program is limited by rdson of the synchronous power fet and current monitoring adc range. for example, using a synchronous fet with rdson of 30m and the wider adc range, the maximum current limit programmed would be: xr77128 samples current approximately 30ns before the synchronous fet turns off, so the actual measured dc out- put current in this example would be 9.33a plus approxi- mately half the inductor ripple. the output current reported by the xr77128 is processed through a seven sample median filter in order to reduce noise. when the ocp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. in addition, ocp fault can be monitored through hw flags on gpio0. the host can also monitor ocp warning flag through hw flags on gpio0. the ocp warning level is calculated by pa 5.2 as 85% of the ocp fault level. a user can choose one of three options in response to an ocp event: shut down the faulting channel, shut down the faulting channel and perform auto-restart of the channel, or restart the chip. choosing the restart chip option during development is not recommended as it makes debug efforts difficult. for the case of shutdown and auto-restart channel, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) peri- ods in 1 ms increments with a maximum value of 255 ms. note: the channel fault action response is the same for an ocp or ovp event. start-up time-out fault a channel will be at startup ti meout fault if it does not come up in the time period specified in the startup time- out box. when the fault is generated, th e host will be notified by the supply_fault_event interrupt generated by the con- ocp max (a) 280 mv 30 m ? ----------------- 9.33 a ==
? 2014 exar corporation xr77128 22 / 28 exar.com/xr77128 rev 1a troller. the host then can use an i 2 c command to check which channel is at fault. ldo5 ocp when current is drawn from ldo5 that exceeds ldo5 cur- rent limit, the controller gets reset. ldoout ocp when current drawn from ldoout exceeds ldoout cur- rent limit the regulator gets shut down, a fault is generated, and the host will be notified by the supply_- fault_event interrupt generated by the controller. the host then can through an i 2 c command check which chan- nel/regulator is at fault. once the fault condition is removed, the host needs to turn the regulator on again. v5ext switchover and control the xr77128 has a function called v5ext that allows an external 5v power supply to be used to supply its internal 5v (ld05) housekeeping voltage instead of using its inter- nal 5v ldo. this function can notably reduce the control- lers power dissipation and improve overall system operating efficiency (particularly in the pfm mode). when enabled in pa5.2, ld05 will automatically switch over to the external supply and disable the internal ldo when the v5ext voltage reaches a programmable threshold volt- age. the switchover thresholds are programmable in 50mv steps with a total range of 200mv. hysteresis to switch the external 5 volt supply in and out is 150mv. ldo5 automati- cally turns off when the external voltage is sw itched in. this is referred to as forward transfer. there are two voltage sequencing requirements to use the v5ext function: 1. power on - the chips vcc voltage has to be applied prior to the v5ext voltage. if the v5ext voltage however is present before vcc is applied, adding a simple logic fet to the v5ext input will meet this requirement. this is described in detail in the operating from a system 5v sec- tion. 2. power off - once the forward transfer is complete, the controllers internal circuits are then operating on the exter- nal 5v supply, so the v5ext voltage has to remain in regu- lation, above the switchover threshold, as long as any output is operating. once all outputs are disabled the v5ext supply can be turn off (off last). this will ensure that no false faults are indicated during shutdown. when using v5ext, an additional good quality 22uf capacitor needs to be placed from the ldo5 pin to ground to filter out any potential noise from getting into the internal analog blocks. if the v5ext function is not used, the v5ext pin should be either grounded or left floating, in conjunction with making sure the function gets disabled through pa 5.2. operating from a generated 5v output it is recommended wh en using the 5vext function, that the 5v rail be generated by one of the xr77128 outputs and routed back to the v5ext pin. this meets the power on sequence requirement. power down sequencing requires that the v5ext supply remains on until the all outputs are powered down. therefore, the 5v rail should be defined in pa 5.2 as the last to be shut down. if the 5v output has no requirement for being actively shut down, then set the active shutdown threshold to 5v. operating from a system 5v the system 5v rail must be regulated to a value of 5v, -5%/ +10% and the v5ext switchover threshold must be set to 4.8v in pa 5.2. vcc must be applied to the chip before connecting the sys- tem 5v to the v5ext pin. if the system 5v rail is an always on rail, a simple way to meet the power on sequencing requirement is to add a logic nfet, with the source con- nected to the v5ext pin, the gate to vcc pin and the drain to the system 5v supply. for proper operation the vcc input voltage must be greater than 5v plus the nfet threshold voltage. in this configuration, the enable pin of the xr77128 should be left floating. again the v5ext sup- ply has to remain on until all the output have been turned off. fault management fault management settings, when v5ext is xr77128 gen- erated require, that the other three rails follow the 5v rail if it faults. there are three fault actions the 5v rail may take: shutdown channel , shutdown and auto-restart channel , and restart chip . if shutdown channel is selected, out- side interaction is required to restart the 5v and the other three rails. this may be through i 2 c, i/os or vcc power cycling. if shutdown and auto-restart channel is selected, to restart the other channels, an i/o should be assigned as hw power good or power ok for the 5v output and con- nected to a second i/o configured to enable for the other three outputs. lastly, restart chip is the simplest to use for auto recovery.
? 2014 exar corporation xr77128 23 / 28 exar.com/xr77128 rev 1a fault management settings when using the system 5v for v5ext require that all outputs have ovp set to 5% with fault action set to restart chip . external clock synchronization xr77128 can be run off an external clock available in the system or another xr77128. the external clock must be in the ranges of 10mhz to 15.5mhz or 20mhz to 31mhz. locking to the external clock is done through an internal phase lock loop (pll) which requires an external loop capacitor of 2.2nf to be connected between the cpll pin and agnd. in applications where this f unctionality is not desired, the cpll capacitor is not necessary and can be omitted, and the pin shall be left floating. in addition, the user needs to make sure the function gets disabled through register set- tings. the external clock must be routed to gpio0. the gpio0 setting must reflect the range of the external clock applied to it: sys_clock/8 corresponds to the range of 10mhz to 15.5mhz while sys_clock/4 setting corresponds to the range of 20mhz to 31mhz. the functionality is enabled in pa 5.2 by selecting external clock-in function under gpio0. when the controller switches over to the external clock, the pll_lock_in interrupt is generated to inform the host. to the contrary, when the controller switches back to the inter- nal clock source, the pll_lock_out interrupt gets gen- erated. clock out xr77128 can supply clock out to be used by another xr77128 controller. the clock is routed out through gpio1 and can be set to the system clock divided by 8 (sys_clock/ 8) or the system clock divided by 4 (sys_clock/4) frequen- cies. the functionality is enabled in pa 5.2 by selecting external clock-out function under gpio1. channel control channels including ldoout can be controlled inde- pendently by any gpio/psio or i 2 c command. channels will start-up or shut-down following transitions of signals applied to gpio/psios set to control the channels. the control can always be overridden with an i 2 c command. regardless of whether the channels are controlled inde- pendently or are in a group, the ramp rates will be followed as specified (see the power sequencing section). regulated voltages and voltage drops across the synchro- nous fet on each switching channel can be read back using i 2 c commands. the regulated voltage read back res- olution is 15mv, 30mv and 60mv per lsb depending on the target voltage range. the voltage drop across the syn- chronous fet read back resolution is 1.25mv and 2.5mv per lsb depending on the range. through an i 2 c command the host can check the status of the channels; whether they are in regulation or at fault. regulated voltages can be dynamically changed on switch- ing channels using i 2 c commands with resolution of 2.5mv, 5mv and 10mv depending on the target voltage range (in pwm mode only). for more information on i 2 c commands refer to anp-38, or contact exar or your local exar representative. power sequencing all four channels and ldoout can be grouped together and will start-up and shut-down in a user defi ned sequence. selecting none means channel(s) will not be assigned to any group and therefore, will be controlled independently. group selection
? 2014 exar corporation xr77128 24 / 28 exar.com/xr77128 rev 1a there are three groups: ? group 0 C is controlled by the chip enable or an i 2 c command. channels assigned to this group will come up with the enable signal being high (plus additional delay needed to load a configuration from flash mem- ory to run-time registers), and will go down with the enable signal being low. the control can always be overridden with an i 2 c command. ? group 1 C can be controlled by any gpio/psio or an i 2 c command. channels assigned to this group will start-up or shut-down following transitions of a signal applied to the gpio/psio set to control the group. the control can always be overridden with an i 2 c command. ? group 2 C can be controlled by any gpio/psio or an i 2 c command. channels assigned to this group will start-up or shut-down following transitions of a signal applied to the gpio/psio set to control the group. the control can always be overridden with an i 2 c command. start-up for each channel within a group a user can specify the fol- lowing start-up characteristics: ? ramp rate C expressed in volts per milliseconds. it does not apply to ldoout. ? order C position of a channel to come-up within the group ? wait pgood? C selecting this option for a channel means the next channel in the order will not start ramp- ing-up until this channel reaches the target level and its power good flag is asserted. ? delay C an additional time delay a user can specify to postpone a channel start-up with respect to the previous channel in the order. the delay is expressed in millisec- onds with a range of 0ms to 255ms. shut-down for each channel within a group a user can specify the fol- lowing shut-down characteristics: ? ramp rate C expressed in volts per milliseconds. it does not apply to ldoout. ? order C position of a channel to come-down within the group ? wait stop thresh? C selecting this option for a channel means the next channel in the order will not start ramp- ing down until this channel reaches the stop threshold level. ? delay C additional time delay a user can specify to post- pone a channel shut-down with respect to the previous channel in the order. the delay is expressed in millisec- onds with a range of 0ms to 255ms. monitoring vcc and temperature through i 2 c commands, the host can read back voltage applied to the vcc pin and the die temperature respec- tively. the vcc read back resolution is 200mv per lsb; the die temperature read back resolution is 5c per lsb. for more on i 2 c commands refer to anp-38. regulating higher than 5.5v to set the output voltage higher than 5.5v, the user needs to add an external voltage divider. the resistors used in the voltage divider should be below 20k. in practice, the pa 5.2 design tool handles all the details and the user only has to enter the desired output volt age. the pa 5.2 tool will rec- ommend resistor divider values which can be modified by the user. external driver mode xr77128 may be configured to drive external drmos or similar devices using the gl pin. although not supported by pa 5.2 as of this publication date, future releases will sup- port this feature. exars technical support team can provide assistance to enable the feature. when the controller is in external driver mode, the pwm signal is internally routed to the gl pin and can be used to directly drive the pwm input of drmos devices according
? 2014 exar corporation xr77128 25 / 28 exar.com/xr77128 rev 1a to the interface schematics shown below. the gh pin is not used in this mode and needs to be left floating. connecting the lx pin to the switch node and the gl_rtn pin to the pgnd (synchronous mosfet source) of the drmos device allows current monitoring, over-current warning and over-current fault operation. the boost cap must be connected between the lx and bst pins to ensure proper biasing of the internal circuitry. if current monitoring is not needed, the lx pin should be grounded. the boost cap will be connected between the bst and lx pins. the pwm output is a 5v signal and does not support tri- state. only ccm operation is recommended. when setting the active shutdown threshold level, using a low value (100mv for instance) to discharge the output capacitors and avoid a possibility of a ne gative ring on the output during shut down is recommended. downloading configuration to xr77128 a key benefit of exars programmable power technology is the ability to easily update the design and chip configura- tion during development. the best way to do this is to pro- gram the ram memory rather than programming the flash nvm. pa 5.2 provides a ram download function accessible through the dashboard or through the tools menu. ram programming requires that there is no valid configura- tion in the flash nvm. a valid configuration is loaded in the chip if in the dashboard window, the reset chip (f8) button is clicked and after a short delay the chip ready indicates yes . when a new configuration is loaded into ram with a chip that already contains a valid configuration in flash nvm, the first step will be to invalidate the flash configuration. the device will be reset to clear the prior ram content and then the new run time configuration gets loaded. pa 5.2 will indicate that it successfully downloaded the configuration to run time registers after which the chip ready indicator will be asserted by pa 5.2 acting as a host. if the configuration changes i 2 c address, the device will respond to the new address at this point. for users that wish to create their own downloading proce- dure, they can refer to anp-39. programming xr77128 once the design has been tested and verified its configura- tion can permanently be saved into flash nvm. xr77128 is a flash based device which means its configu- ration can be programmed into flash nvm and re-pro- grammed a number of times. programming of flash nvm is done through pa 5.2. by clicking on the flash button, user will start programming sequence of the design configuration into the flash nvm. after the programming sequence completes, the chip will
? 2014 exar corporation xr77128 26 / 28 exar.com/xr77128 rev 1a reset (if the automatically reset after flashing box is checked), and boot the design configuration from the flash. for users that wish to create their own programming proce- dure so they can re-program flash in-circuit using their sys- tem software, they should contact exar for a list of i 2 c flash commands needed or refer to anp-38. enabling xr77128 xr77128 has an internal pull-up ensuring it gets enabled as soon as internal voltage supplies have ramped up and are in regulation. driving the enable pin low externally will keep the controller in the shut-down mode. a simple open drain pull down is the recommended way to shut xr77128 down. if the enable pin is driven high externally to control xr77128 coming out of the shut-down mode, care must be taken in such a scenario to ensure the enable pin is driven high after vcc gets supplied to the controller. a diode in series with a resistor between the ldo5 and enable pins may offer a way to more quickly pull down the ldo5 output when the enable pin is pulled low. in the application where vcc = ldo5 = 4.75v to 5.5v, dis- abling the device by pulling th e enable pin low is not rec- ommended. it is recommended to leave the enable pin floating and place the controller in the standby mode instead. the standby mode is defined as the state when all switching channels and ldoout are disabled, all ios pro- grammed as inputs, and the system clock is disabled. in this state the device consumes 550ua typical. application information thermal design as a four channel controller with internal mosfet drivers and 5v gate drive supply all in one 7x7mm 44pin tqfn package, there is the potential for the power dissipation to exceed the package thermal limitations. the xr77128 has an internal ldo which supplies 5v to the internal circuitry and mosfet drivers during startup. it is generally expected that either one of the switching regulator outputs is 5v or another 5v rail is available in the system and con- nected to the v5ext pin. if there is no 5v available in the system, then the power loss w ill increase significantly and proper thermal design becomes critical. for lower power levels using properly sized mosfets, the use of the inter- nal 5v regulator as a gate drive supply may be appropriate. layout guidelines refer to application note anp-32 practical layout guide- lines for powerxr designs .
? 2014 exar corporation xr77128 27 / 28 exar.com/xr77128 rev 1a mechanical dimensions 44-pin tqfn

? 2014 exar corporation xr77128 28 / 28 exar.com/xr77128 rev 1a for further assistance: technical support: techsupport.exar.com technical documentation: www.exar.com/techdoc exar corporation headquarters and sales offices 48720 kato road tel.: +1 (510) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 668-7001 notice exar corporation reserves the right to make changes to the produc ts contained in this publication in order to improve design, p erformance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no re sponsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its product s in life support applications where the failure or malfunctio n of the product can reasonably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. products are not authorized fo r use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user as sumes all such risks; (c) potential liability of exar cor- poration is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. ordering information yy = year (last two digits); ww = work week; x = lot number; when applicable revision history part number package green operating temperature range packaging marking default i 2 c address xr77128elb-f 44-pin tqfn yes -40c to +125c tr ay xr77128elb yywwf xxxxxxxx 0x28 (7-bit) xr77128elbtr-f tape and reel xr77128elbmtr-f mini tape and reel xr77128evb-demo-1 xr77128 evaluation board XR77128EVB-DEMO-1-KITA the demonstration kit includes an xr77128 evaluation board with powerarchitect software and controller bo ard. revision date description 1a december 2014 initial release

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